DIPSYLAN

Distributed PBX Development System With LAN Interconnection

Funded under 5th FWP (Fifth Framework Programme)

Action Line: Peripherals, sub-systems and microsystems - Subsystems technologies

Coordinator
Contact Person: Name: Doumenis, Gregory 
Tel: +30-210-9858816 
Fax: +30-210-9858817 
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Organisation: 
Global Digital Technologies S.A. 
Eirinis Avenue 65 
48100   Preveza 
GREECE

The DIPSYLAN ("Distributed PBX with LAN interconnection") is a single contractor first user action (FUSE) project. The duration of the project was 14 months (September 1st, 2000 until October 31st, 2001). Global Digital Technologies SA (GR) (GDT) is the coordinator of the project. According to the FUSE framework, GDT subcontracted technology provision and transfer activities to SIDSA (ES) and NTUA (GR). 
The objective of DIPSYLAN is to enhance GDT's technical capabilities and business process in such way that, by the end of the project, the design, development and delivery of complete prototypes of telecommunications subsystems comprising of both hardware and software would be possible. 
The focus of DIPSYLAN was in the acquisition of know-how for the development of H/W subsystems and in the adoption of correct business processes for the cost-effective production of prototype and small volume H/W subsystems (at printed circuit board level). 

Objectives: 
The DIPSYLAN project objectives are summarized as follows: 
Acquire technology in the area of H/W design and prototyping. 
Optimally use the acquired technology through the revision of the company's business process. 
Carry-out the DIPSYLAN baseline project (DeReGate) 

Work description: 
The baseline project designed a low cost, compact system with H/W and S/W prototyping capabilities, able to support the development of SOHO communications applications (Intelligent NT, Small PBX, Router, Information gateway etc.) The board integrates the necessary processing capacity and interface support to facilitate S/W development and integration, as well as prototype application demonstration under realistic configurations and system conditions. Low cost and realistic system configuration was achieved with the integration of state of the art components (mainly from Infineon Technologies AG). 
The board is easily extendable and different interface configurations can be supported. DeReGate can function as a "proof of concept" demonstrator for system level definition and application S/W integration for future IC products. 

The DeReGate embeds the following interfaces: 

2 Ethernet 10/100 BASE-T interfaces. 
2 UART interfaces (1 multiplexed with IrDA). 
1 ATM UTOPIA (Level 1/Level 2) interface. 
2 Analogue (t/r) telephone interfaces. 
2 ISDN S/T interfaces. 
3 ISDN Up interfaces. 
1 PRI interface (E1/T1). 
1 SHDSL. 
1 USB host/device 
Extension connectors: 
4 x PCM 
1 x IOM-2000 
1 x IOM-2 
1 x µP bus 

Milestones: 
Throughout the project, major milestones were associated with project deliverables. The deliverables that have been produced are: 

M1 - D1: "Development procedures and tool selection". 
M2 - D2a: "Draft quality manual". 
M3 - D3: "Detailed system specifications". 
M4 - D4: "Interim project report". 
M5 - D5: "Report on design and implementation". 
M6 - D6: "DIPSYLAN H/W prototype". 
M7 - D2b: "Final quality manual". 
M8 - D7: "DIPSYLAN Demonstration". 
M9 - D8: "Dissemination report". 
M10 - D9: "Final Project report". 
All milestones were met with minor delays and the associated material was produced as planned. Milestone M3 (associated with D3) concluded the specification phase and enabled full-scale design of the DIPSYLAN (DeReGate) board. The main features of the system remain unchanged: 

Telecommunications systems development system. 
Tailored for residential / SOHO applications. 
Integrates traditional with emerging network interfaces. 
Connects to both telecom and datacom networks. 
Suitable for telecom software development. 
Allows "proof of concept" application demonstration prior to VLSI SoC implementation. 
The specifications obtained are very close to the ones foreseen during the preparation of the project. This verifies the correctness of the original concept. Differences are mainly in the dimensioning of the embedded interfaces and in the incorporation of the CARMEL subsystem, which offers the necessary DSP capacity to implement native VoIP functionality. 

MMilestone M7 (associated with D2b) presented GDT's Quality System for the Design, Development, Production and Support of high technology products and consultant services for communication systems and services. 
Milestone M9 (associated with D8) concluded the actions needed in order to improve the visibility of the project's results. This includes the hosting of the official DIPSYLAN Web page and presentation of the DeReGate board in major events.

Project details
Project Acronym: DIPSYLAN 
Project Reference: IST-1999-20337 
Start Date: 2000-08-24 
Duration: 14 months 
Project Cost: 164400.00 euro 
Contract Type: Preparatory, accompanying and support measures 
End Date: 2001-10-23 
Project Status: Completed 
Project Funding: 100000.00 euro 

MEMSENSE project

GDT announces  the successful completion of the MEMSENSE RTD project Memsense site 

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